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A6219DS
Dual Full-Bridge PWM Motor Driver
Features and Benefits
Interchangeable with SGS L6219DS 750 mA Continuous Output Current 45 V Output Sustaining Voltage Internal Clamp Diodes Internal PWM Current Control Low Output Saturation Voltage Internal Thermal Shutdown Circuitry Similar to Dual PBL3717, UC3770
Description
The L6219DS motor driver is designed to drive both windings of a bipolar stepper motor or bidirectionally control two DC motors. Both bridges are capable of sustaining 45 V and include internal pulse-width modulation (PWM) control of the output current to 750 mA. The outputs have been optimized for a low output saturation voltage drop (less than 1.8 V total source plus sink at 500 mA). For PWM current control, the maximum output current is determined by user selection of a reference voltage and sensing resistor. Two logic-level inputs select output current limits of 0, 33, 67, or 100% of the maximum level. A PHASE input to each bridge determines load current direction. The bridges include both ground clamp and flyback diodes for protection against inductive transients. Internally generated delays prevent crossover currents when switching current direction. Special power-up sequencing is not required. Thermal protection circuitry disables the outputs if the chip temperature exceeds safe operating limits. The L6219DS is supplied in a 24-pin surface-mountable SOIC, with 4 internally-fused leads for maximum package power dissipation in the smallest possible construction. It is lead (Pb) free with 100% matte tin leadframe plating.
Package: 24 pin SOICW (suffix LB)
Not to scale
Typical Application
STEPPER MOTOR
1 2 RS RC C
C
VBB
V 24 23 RS RC 22 21 20 19 18 17 FROM P CC +
BB
3 4 5 6 7 8 2
1
FROM P
99
PWM 1
1
16 15 14 820 pF V
10 V
REF
2
PWM 2
REF
11 12 820 pF CT VCC
13 +5 V
C
56 k RT
T
56 k RT
Dwg. EP-008B1
29319.43H
L6219DS
Selection Guide
Part Number
L6219DS-T L6219DSTR-T
Dual Full-Bridge PWM Motor Driver
Packing
31 pieces per tube 1000 pieces per reel
Operating Ambient Temperature Range TA (C)
-20 to 85 -20 to 85
Absolute Maximum Ratings
Characteristic Motor Supply Voltage Logic Supply Voltage Logic Input Voltage Range Output Emitter Voltage Output Current, Peak Symbol VBB VCC VIN VSENSE IOUT(pk) Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified peak current rating or a junction temperature of +150C. Range S Notes Rating 45 7.0 -0.3 to VCC+0.3 1.5 1.0 Units V V V V A
Output Current, Continuous
IOUT
750
mA
Operating Ambient Temperature Maximum Junction Temperature Storage Temperature
TA TJ(max) Tstg
-20 to 85 150 -55 to 150
C C C
Thermal Characteristics
Characteristic Package Thermal Resistance Symbol RJA RJT *Additional thermal information available on the Allegro website.
2.5
Test Conditions* 1-layer PCB with copper limited to solder pads 1-layer PCB with 3.57 in.2 of copper area
Value Units 77 49 6 C/W C/W C/W
R JT = 6C/W
2.0
1.5
R JA= 49C/W
1.0
0.5
R JA= 77C/W
0 25 50 75 100 125 150
Dwg. GP-019C
TEMPERATURE in C
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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L6219DS
Dual Full-Bridge PWM Motor Driver
PWM Current-Control Circuitry
CHANNEL 1 TERMINAL NUMBERS SHOWN. VBB
24
Phase Truth Table
PHASE H L OUTA H L OUTB L H
OUT B
1 21
OUT A V REF 15 20 k 10 40 k I 0 20 I 1 17 10 k RS
23
SENSE COMP IN -
22
+
CC
ONE SHOT
14
SOURCE DISABLE
RC
RC
RT
CT
Dwg. EP-007-5
Pin-Out Diagram
OUT 1A OUT 2A SENSE 2 COMP IN 2 OUT 2B GROUND GROUND I 02 I12 PHASE 2 V REF 2 RC 2 1 2 3 4 5 6 7 8 2 1 VBB 24 23 22 21 20 19 18 17 LOAD SUPPLY SENSE 1 COMP IN 1 OUT 1B I 01 GROUND GROUND I11 PHASE 1 V REF 1 RC 1 LOGIC SUPPLY
PWM 1
9
1
16 15 14
10 11 12
2
PWM 2
V CC
13
Dwg. PP-005-3
Copyright (c) 1998, 2003 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
3
L6219DS
Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25C, TJ 150C, VBB = 45 V, VCC = 4.75 V to 5.25 V, VREF = 5.0 V (unless otherwise noted).
Limits Characteristic Output Drivers (OUTA or OUTB) Motor Supply Range Output Leakage Current VBB ICEX VOUT = VBB VOUT = 0 Output Sustaining Voltage Output Saturation Voltage VCE(sus) VCE(SAT) IOUT = 750 mA, L = 3.0 mH Sink Driver, IOUT = +500 mA Sink Driver, IOUT = +750 mA Source Driver, IOUT = -500 mA Source Driver, IOUT = -750 mA Clamp Diode Leakage Current Clamp Diode Forward Voltage Driver Supply Current IR VF IBB(ON) IBB(OFF) Control Logic Input Voltage VIN(1) VIN(0) Input Current IIN(1) All inputs All inputs VIN = 2.4 V VIN = 0.8 V Reference Voltage Range Current Limit Threshold (at trip point) VREF VREF / VCOMPIN Operating I0 = I1 = 0.8 V I0 = 2.4 V, I1 = 0.8 V I0 = 0.8 V, I1 = 2.4 V Thermal Shutdown Temperature Total Logic Supply Current TJ ICC(ON) ICC(OFF) Fixed Off-Time toff I0 = I1 = 0.8 V, No Load I0 = I1 = 2.4 V, No Load RT = 56 k, CT = 820 pF 2.4 -- -- -- 1.5 9.5 13.5 25.5 -- -- -- -- -- -- <1.0 - 3.0 -- 10 15 30 170 40 10 46 -- 0.8 20 -200 7.5 10.5 16.5 34.5 -- 50 14 -- V V A A V -- -- -- C mA mA s VR = 45 V IF = 750 mA Both Bridges On, No Load Both Bridges Off 10 -- -- 45 -- -- -- -- -- -- -- -- -- < 1.0 <-1.0 -- 0.4 1.0 1.0 1.3 < 1.0 1.6 20 5.0 45 50 -50 -- 0.6 1.2 1.2 1.5 50 2.0 25 10 V A A V V V V V A V mA mA Symbol Test Conditions Min. Typ. Max. Units
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
4
L6219DS
Dual Full-Bridge PWM Motor Driver
Applications Information
PWM Current Control
The L6219DS dual bridge is designed to drive both windings of a bipolar stepper motor. Output current is sensed and controlled independently in each bridge by an external sense resistor (RS), internal comparator, and monostable multivibrator. When the bridge is turned on, current increases in the motor winding and it is sensed by the external sense resistor until the sense voltage (VCOMPIN) reaches the level set at the comparator's input: ITRIP = VREF/10 RS The comparator then triggers the monostable which turns off the source driver of the bridge. The actual load current peak will be slightly higher than the trip point (especially for lowinductance loads) because of the internal logic and switching delays. This delay (td) is typically 2 s. After turn-off, the motor current decays, circulating through the ground-clamp diode and sink transistor. The source driver's off time (and therefore the magnitude of the current decrease) is determined by the monostable's external RC timing components, where toff = RTCT within the range of 20 k to 100 k and 100 pF to 1000 pF. The fixed-off time should be short enough to keep the current chopping above the audible range (< 46 s) and long enough to properly regulate the current. Because only slow-decay current control is available, short off times (< 10 s) require additional efforts to ensure proper current regulation. Factors that can negatively affect the ability to properly regulate the current when using short off times include: higher motor-supply voltage, light load, and longer than necessary blank time. When the source driver is re-enabled, the winding current (the sense voltage) is again allowed to rise to the comparator's threshold. This cycle repeats itself, maintaining the average motor winding current at the desired level. Loads with high distributed capacitances may result in high turn-on current peaks. This peak (appearing across RS) will attempt to trip the comparator, resulting in erroneous current control or high-frequency oscillations. An external RCCC time delay should be used to further delay the action of the comparator. Depending on load type, many applications will not require these external components (SENSE connected to COMP IN).
V P HAS E
PWM Output Current Wave Form
+ I OUT 0 -
I T R IP
td
toff
Dwg. WM-003-1A
Load Current Paths
V BB
RS
B R IDG E ON S OUR C E OF F ALL OF F
Dwg. E P -006-1
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
5
L6219DS
Dual Full-Bridge PWM Motor Driver
Logic Control of Output Current
Two logic level inputs (I0 and I1) allow digital selection of the motor winding current at 100%, 67%, 33%, or 0% of the maximum level per the table below. The 0% output current condition turns off all drivers in the bridge and can be used as an OUTPUT ENABLE function. These logic level inputs greatly enhance the implementation of P-controlled drive formats. During half-step operations, the I0 and I1 allow the P to control the motor at a constant torque between all positions in an eightstep sequence. This is accomplished by digitally selecting 100% drive current when only one phase is on and 67% drive current when two phases are on. Logic highs on both I0 and I1 turn off all drivers to allow rapid current decay when switching phases. This helps to ensure proper motor operation at high step rates. The logic control inputs can also be used to select a reduced current level (and reduced power dissipation) for `hold' conditions and/or increased current (and available torque) for start-up conditions. Current-Control Truth Table
l0 L H L H I1 L L H H Output Current VREF/10 RS = ITRIP VREF/15 RS = 2/3 ITRIP VREF/30 RS = 1/3 ITRIP 0
General
The PHASE input to each bridge determines the direction motor winding current flows. An internally generated dead time (approximately 2 s) prevents crossover currents that can occur when switching the PHASE input. All four drivers in the bridge output can be turned off between steps (I0 = I1 2.4 V) resulting in a fast current decay through the internal output clamp and flyback diodes. The fast current decay is desirable in half-step and high-speed applications. The PHASE, I0 ,and I1 inputs float high. Varying the reference voltage (VREF) provides continuous control of the peak load current for microstepping applications. Thermal protection circuitry turns off all drivers when the junction temperature reaches 170C. It is only intended to protect the device from failures due to excessive junction temperature and should not imply that output short circuits are permitted. The output drivers are re-enabled when the junction temperature cools to 145C. The L6219DS output drivers are optimized for low output saturation voltages--less than 1.8 V total (source plus sink) at 500 mA. Under normal operating conditions, when combined with the excellent thermal properties of the fused internal lead package design, this allows continuous operation of both bridges simultaneously at 500 mA.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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L6219DS
Dual Full-Bridge PWM Motor Driver
Application Information
for the given level of ILOAD. The value for RJT is approximately 6C/W. The power dissipation can be improved 20% to 30% by adding a section of printed circuit board copper (typically 6 to 18 square centimeters) connected to the power pins of the device. The thermal performance in applications that run at high load currents, high duty cycles, or both can be improved by adding external diodes from each output to ground in parallel with the internal diodes. Fast-recovery (200 ns) diodes should be used to minimize switching losses. Load Supply Terminal The load supply terminal, VBB, should be decoupled with an electrolytic capacitor (47F is recommended), placed as close to the device as is physically practical. To minimize the effect of system ground IR drops on the logic and reference input signals, the system ground should have a low-resistance return to the load supply voltage. Fixed Off-Time Selection With increasing values of tOFF, switching losses decrease, lowlevel load current regulation improves, EMI reduces, PWM frequency decreases, and ripple current increases. The value of tOFF can be chosen for optimization of these parameters. For applications where audible noise is a concern, typical values of tOFF should be chosen in the range of 15 to 35 s.
Current Sensing To minimize current sensing inaccuracies caused by ground trace IR drops, each current-sensing resistor should have a separate return to the ground terminal of the device. For low-value sense resistors, the IR drops in the PCB can be significant and should be taken into account. The use of sockets should be avoided as their contact resistance can cause variations in the effective value of RS. Generally, larger values of RS reduce the aforementioned effects but can result in excessive heating and power loss in the sense resistor. The selected value of RS should not cause the absolute maximum voltage rating of 1.5 V, for the SENSE terminal, to be exceeded. The recommended value of RS is in the range of: RS = 0.75 / ITRIP(max) 50% . If desired, the reference input voltage can be filtered by placing a capacitor from REFIN to ground. The ground return for this capacitor as well as the bottom of any resistor divider used should be independent of the high-current power-ground trace to avoid changes in REFIN due to IR drops. Thermal Considerations For reliable operation, it is recommended that the maximum junction temperature be kept below 110C to 125C. The junction temperature can be measured best by attaching a thermocouple to the power pins (6, 7, 18 and 19) of the device and measuring the pin temperature, TTAB. The junction temperature can then be approximated by using the formula: TJ = TTAB + (2 x ILOAD x VF x RJT) , where VF can be chosen from the electrical specification table
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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L6219DS
Dual Full-Bridge PWM Motor Driver
Package LB, 24-Pin SOICW
15.400.20 4 4 24 2.20 +0.07 0.27 -0.06
9.60 A
7.500.10
10.300.33 +0.44 0.84 -0.43
1 0.65
B PCB Layout Reference View
2 0.25 C SEATING PLANE GAUGE PLANE
1.27 24X 0.10 C 0.41 0.10 1.27 A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-24M)
SEATING PLANE 2.65 MAX 0.20 0.10
For reference only Pins 6 and 7, and 18 and 19 internally fused (Reference JEDEC MS-013 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances
Copyright (c)1998-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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